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Computer
Engineering II
Exam details
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Questions:
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Attempt any 4 questions from 6
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Time:
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3 hours
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Location:
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Wed 06 June 2001 , 1300 - 1600, Craiglockhart [Link]
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Exam coverage
The following defines the coverage of FOUR of the SIX questions in the Computer Engineering II exam (the other TWO are set by A.Armitage):
1. Cache Architecture (Chapter 5)
No:
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Description
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Section
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1.1
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Understands the basic architecture of a cache
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5.4
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1.2
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Defines the different types of cache architures
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5.4.1
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1.3
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Understands the requirements for cache coherency and snooping
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5.4.2
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1.4
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Defines the requirements for the MESI protocol
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5.4.7
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1.5
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Outlines the architecture of a basic cache system, showing cache directory and memory entries
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5.4.4
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1.6
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Defines the requirements for each of the states of the MESI protocol
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5.4.7
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No:
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Description
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Section
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2.1
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Understands the basic architecture of DRAM, and the associated interface lines.
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12.2
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2.2
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Outlines the method used to address DIMMs
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12.2
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2.3
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Outlines the signal differences between SDRAM and EDO
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Table 12.1
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2.4
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Defines how the access time of DRAM varies, such as the definition of 5-2-2-2.
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12.2
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2.5
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Outlines the differences between different types of DRAM, such as EDO, SRAM, FPM and SDRAM.
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12.2.1, 12.2.2, 12.2.3
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2.6
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Defines the timing requirements for acessing memory
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2.7
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Understands and defines the architecture of Direct RDRAM.
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12.2.5
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No:
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Description
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Section
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3.1
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Outlines the main types of SCSI and their
performance
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To be updated
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3.2
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Identifies the main SCSI data and signal lines
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3.3
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Identifies the main SCSI data and signal lines
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3.4
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Describes the importance and usage of ID numbers
of the SCSI bus
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3.5
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Describes how arbitration occurs on the SCSI bus
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3.6
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Describes the main phases that occur on the SCSI
bus
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3.7
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Understands the importance of time-outs on the
SCSI bus
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No:
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Description
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Section
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4.1
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Explains the basic operation of the PCI bus
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18.2
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4.2
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Explains multiplexed and burst modes of the PCI
bus
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18.2
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4.3
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Derives the maximum throughput for multiplexed
and burst modes of the PCI bus
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4.4
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Identifies the main data and handshaking signals
on the PCI bus
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Table 18.1, 18.12
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4.5
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Identifies the main PCI bus cycles and how they
are identified
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4.6
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Outlines the concept of bus mastering and how PCI
uses it
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4.7
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Outlines the usage of the PCI command cycle
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18.8
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4.8
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Outlines how bus arbitration and device locking is achieved on the
PCI bus
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18.3
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5. Motherboard/Hub-based (Chapter 27 and 28)
No:
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Description
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Section
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5.1
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Identifies the main data, address and control signals used by the Pentium to communicate with other devices.
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To be updated
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5.2
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Outlines the architecture of a north/south bridge system, identifying the main handshaking lines
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5.3
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Contrasts different Intel chipsets (440/450 and 810/820/840)
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Table 28.1
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5.4
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Outlines the architecture of a hub-based system (especially the 810/820/840 chipset)
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28.1, 28.2, 28.3
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5.5
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Contrasts north/south bridge architecture with hub-based systems, and identifies typical transfer rates for interfaces (such as IDE, AGP, PCI, and so on).
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